About this tool
The Logic Gate & Circuit Simulator runs a real discrete-event simulation, not a static truth-table evaluator. Every gate, latch and flip-flop has a propagation delay; changes ripple through the netlist as timed events on a priority queue, so you can watch a signal actually take several ticks to cross a chain of gates the way it would on real silicon.
Signals carry four values — 0, 1, Z (high-impedance) and X (unknown/conflict) — so tri-state buffers and driver conflicts behave correctly: two outputs fighting over the same net are detected and flagged rather than silently resolved to whichever wire was drawn last.
Beyond gates (AND/OR/NAND/NOR/XOR/XNOR/NOT/BUFFER/TRISTATE), the palette includes SR and D latches, D flip-flops with configurable clock edge, 2:1 and 4:1 multiplexers, switches and clocks as sources, and OUTPUT/seven-segment sinks — enough to wire adders, counters and small state machines from scratch.
For purely combinational circuits, the tool derives a full truth table and a Karnaugh map with Quine-McCluskey minimization, giving you both the brute-force behavior and the simplified Boolean expression side by side.
When you're ready to leave the browser, export the circuit as Verilog, VHDL, an annotated JSON netlist (with a documented schema for round-tripping), or an SVG schematic reflecting live signal colors.
How to use
Place components
Click a palette entry, then click the canvas to drop it; click again to cancel placement.
Wire pins
Click an output pin, then an input pin, to connect them; clicking the same pin twice cancels the pending wire.
Toggle inputs
Click an INPUT switch to flip it between 0 and 1 while the simulation runs.
Run or step
Run advances the simulator continuously; Step advances exactly one event tick for precise timing inspection.
Edit properties
Select a component to adjust its propagation delay, input count, clock period or flip-flop edge in the side panel.
Read the outputs
Switch to the Truth Table or K-Map tab for combinational circuits, or Export for Verilog/VHDL/SVG/JSON.
Use cases
Digital logic coursework
Build the exact circuit from a homework problem and read off its truth table or minimized K-Map instead of hand-deriving both.
Interview prep
Prototype adders, muxes and small state machines live, then verify propagation and driver conflicts before whiteboarding them.
HDL bootstrapping
Sketch a small module visually, export Verilog or VHDL as a starting point, then continue in your normal toolchain.
Teaching tri-state buses
Deliberately create a driver conflict to show students what bus contention looks like and why enable lines matter.
Common mistakes
Mistake:Expecting a static truth table for clocked circuits
Fix:Circuits with CLOCK, DFF or latch elements depend on prior state and timing — the Truth Table tab warns and still shows a snapshot, but Step through the simulation instead to see real behavior.
Mistake:Wiring two outputs to the same input pin
Fix:Each input pin accepts one wire; to combine signals, use a gate (OR, MUX) or a tri-state bus with enable lines, not two direct wires.
Mistake:Ignoring propagation delay when reading the canvas
Fix:A newly wired gate doesn't show its output instantly — Step or Run to let the event queue settle before judging the result.
Mistake:Building more than 10 input variables
Fix:Truth tables and K-Maps cap at 10 and 6 input variables respectively (2^10 rows, readable K-Map grid) — beyond that, verify behavior by stepping the simulation instead.
Frequently asked questions
Related guides
Split-Brain Is a Math Problem: Quorums, Circuit Breakers and Chaos Engineering, Simulated
Why 'majority of replicas' is the entire safety argument behind Raft, how a circuit breaker's three states stop one slow dependency from taking down everything upstream, and what happens when you partition a database on purpose.
Why Your Logic Circuit Needs a Clock: Discrete-Event Simulation, Explained
A truth table tells you the answer eventually — it can't tell you when. Propagation delay, tri-state conflicts and the priority-queue trick that makes a browser-based circuit simulator behave like real silicon.
References & standards
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